Technical Field
The present disclosure relates to patterning of electrical structures, and more particularly to forming lines and vias corresponding to underlying metal features.
Description of the Related Art
The fabrication of Very-Large Scale Integrated (VLSI) or Ultra-Large Scale Integrated circuit (ULSI) requires metallic wiring that connects individual devices in a semiconductor chip, to one another. One method of creating this wiring network on such small scale is a dual damascene (DD) process. In a typical DD process, an interlayer dielectric (ILD) typically comprising two dielectric layers (e.g., a via level dielectric and a line level dielectric) is formed on a substrate. In general, the via and line level dielectrics can be made of the same or different insulating films and in the former case applied as a single monolithic layer. A hard mask layer is optionally employed to facilitate etch selectivity and to serve as a polish stop. The wiring interconnect network consists of two types of features: line features that traverse a distance across the chip, and via features which connect lines in different levels together. Decreasing the critical dimensions (CD) and minimum pitch of features in a nanoscale pattern used to fabricate integrated circuits (ICs) increases the density of devices on a chip. Decreasing critical dimensions and minimum pitch further into the nanoscale realm requires advanced patterning methodologies.